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IP4853CX24
SD, MMC and microSD memory card integrated level shifter with PSU, EMI filter and ESD protection
Rev. 02 -- 15 June 2009 Product data sheet
1. Product profile
1.1 General description
The IP4853CX24 is a device that fully integrates a bidirectional level shifter or voltage translator, EMI filter and ESD protection diodes. It is specifically designed to be used for memory card interfaces such as SD, microSD and MultiMediaCard (MMC) memory cards. The integrated power supply unit supplies memory cards with 2.9 V directly from the battery. This enables a 1.8 V operating host-side device (e.g. a processor interface) to communicate with a 2.9 V compliant memory card using its integrated level shifter. Radiation from digital signals in the higher harmonics, close to typical mobile phone frequencies, is suppressed by the EMI filter. The IP4853CX24 is fabricated using monolithic silicon technology in a Wafer Level Chip-Scale Package (WLCSP) with 0.4 mm pitch.
1.2 Features
I I I I I I Dark Green compliant. Pb-free, RoHS compliant Integrated EMI filters Feedback channel for clock synchronization Integrated ESD protection according to IEC 61000-4-2, level 4 WLCSP with 0.4 mm pitch
1.3 Applications
I SD memory card, microSD memory card and MMC interfaces in latest electronic appliances such as: N Mobile phone or smart phone N Digital camera N Card reader in (laptop) computer I Appliances requiring one or several of the following features: N Level shifting and voltage translation from 1.8 V to 2.9 V and from 2.9 V to 1.8 V N ESD protection according to IEC 61000-4-2, level 4 N Power supply regulation from battery to 2.9 V card memory voltage N EMI filtering N Integration of interface-specific biasing resistor network
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
2. Pinning information
2.1 Pinning
bump A1 index area 1 A 2
IP4853CX24
3 4 5
B
C
D
E
001aah951
Transparent top view
Fig 1. Table 1. Pin A1 B1 C1 D1 E1
Pin configuration for WLCSP24 package Pin allocation table Pin A2 B2 C2 D2 E2 Symbol DIR_CMD n.c. ENABLE CMD_H CLK_FB Pin A3 B3 C3 D3 E3 Symbol DIR_0 VCC GND CD DIR_1_3 Pin A4 B4 C4 D4 E4 Symbol VBAT VSD GND CMD_SD WP Pin A5 B5 C5 D5 E5 Symbol DATA2_SD DATA3_SD CLK_SD DATA0_SD DATA1_SD
Symbol DATA2_H DATA3_H CLK_IN DATA0_H DATA1_H
2.2 Pin description
Table 2. Symbol[1] DATA2_H DIR_CMD DIR_0 VBAT DATA2_SD DATA3_H n.c. VCC VSD DATA3_SD CLK_IN
IP4853CX24_2
Pin description Pin A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 Type[2] I/O I I S I/O I/O S O I/O I Description data 2 input or output on host-side direction control input for command direction control input for data 0 supply voltage from battery for regulator data 2 input or output on memory card-side data 3 input or output on host-side not connected supply voltage for host-side circuits output supply voltage for memory card data 3 input or output on memory card-side clock signal input
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
2 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
Pin description ...continued Pin C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 Type[2] I S S O I/O I/O O I/O I/O I/O O I O I/O Description device enable input supply ground supply ground clock signal output on memory card-side data 0 input or output on host-side command input or output on host-side card detect switch biasing output command input or output on memory card-side data 0 input or output on memory card-side data 1 input or output on host-side clock feedback output to host direction control input for data 1, data 2 and data 3 write protect switch biasing output data 1 input or output on memory card-side
Table 2. Symbol[1] ENABLE GND GND CLK_SD DATA0_H CMD_H CD CMD_SD DATA0_SD DATA1_H CLK_FB DIR_1_3 WP DATA1_SD
[1] [2]
The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards. I = input, O = output, I/O = input and output, S = power supply.
3. Ordering information
Table 3. Ordering information Package Name IP4853CX24 Description Version IP4853CX24 WLCSP24 wafer level chip-size package; 24 bumps; 2.01 x 2.01 x 0.61 mm Type number
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
3 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
4. Block diagram
host side VBAT A4 VOLTAGE REGULATOR
R1
SD card side B4 VSD
CLK_IN CLK_FB
C1 E2
C5
CLK_SD
DIR_CMD
A2
R10 R2
D4
CMD_SD
CMD_H
D2
DIR_0
A3
R11 R3
D5
DATA0_SD
DATA0_H
D1
DIR_1_3
E3
R12 R4
E5
DATA1_SD
DATA1_H
E1
R13 R5
A5
DATA2_SD
DATA2_H
A1
R6
B5
DATA3_SD
DATA3_H
B1
VCC ENABLE
B3 C2
R14 R15
R7
C3, C4 E4 D3
GND WP CD
IP4853CX24
001aah980
Fig 2.
Block diagram
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
4 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
5. Functional description
5.1 Logic control signals
Table 4. Control signal truth table VBAT 2.7 V. Control Pin DIR_CMD DIR_0 DIR_1_3 Level[1] H L H L H Host-side Pin CMD_H CMD_H DATA0_H DATA0_H DATA1_H, DATA2_H, DATA3_H DATA1_H, DATA2_H, DATA3_H CLK_FB CMD_H DATA0_H DATA1_H, DATA2_H, DATA3_H CLK_FB Function input output input output input Memory card-side Pin CMD_SD CMD_SD DATA0_SD DATA0_SD DATA1_SD, DATA2_SD, DATA3_SD DATA1_SD, DATA2_SD, DATA3_SD CLK_SD CMD_SD DATA0_SD DATA1_SD, DATA2_SD, DATA3_SD CLK_SD Function output input output input output
Pin ENABLE = HIGH and VCC 1.62 V
L
output
input
DIR_CMD DIR_0 DIR_1_3
X X X
output high-Z high-Z high-Z
output high-Z high-Z high-Z
Pin ENABLE = LOW or VCC 0.8 V
[1]
-
high-Z
high-Z
H = HIGH; L = LOW and X = don't care.
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
5 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
6. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VBAT VI Parameter supply voltage battery supply voltage input voltage 4 ms transient operating at I/O pins 4 ms transient operating Ptot Tstg Tamb VESD total power dissipation storage temperature ambient temperature electrostatic discharge voltage pin VBAT and all memory card-side pins to ground; according to IEC 61000-4-2, level 4 contact air discharge all other pins to ground; according to IEC 61340-3-1, human body model 8000 15000 2000 V V V Tamb = -30 C to +70 C -0.5 -0.5 -55 -30 +5.5 +5.0 550 +150 +85 V V mW C C Conditions Min -0.5 -0.5 -0.5 Max +3.5 +5.5 +5.0 Unit V V V
7. Recommended operating conditions
Table 6. Symbol VCC VBAT VI VO Operating conditions Parameter supply voltage battery supply voltage input voltage output voltage host-side memory card-side; VBAT 3.2 V active mode; pin ENABLE = HIGH host-side memory card-side t/V time difference over voltage change host-side; between 0.2VCC and 0.7VCC memory card-side; between 0.2VO(reg) and 0.7VO(reg) 0 0 VCC VO(reg) 2 2 V V ns/V ns/V Conditions Min 1.62 2.7[1] 0 0 Max 2.1 5.0 2.1 2.9 Unit V V V V
[1]
The device is still fully functional, but the voltage on pin VSD might drop below the recommended memory card supply voltage.
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
6 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
8. Static characteristics
Table 7. Static characteristics At recommended operating conditions; Tamb = -30 C to +85 C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Voltage regulator output: pin VSD VO(reg) regulator output voltage CL = 1 F IO(reg) = 0 A IO(reg) = 200 mA; VBAT 2.9 V Vdo(reg) regulator dropout voltage variation IO(reg) IO(sc) Iq(reg) regulator output current short-circuit output current regulator quiescent current pin ENABLE = HIGH (active mode) pin ENABLE = LOW (not active mode) Cext external capacitance recommended capacitor at pin VSD Control and data inputs Host-side: pins ENABLE, DIR_0, DIR_1_3, DIR_CMD, CLK_IN and DATA0_H to DATA3_H VIH VIL Cch VIH VIL Cch HIGH-level input voltage LOW-level input voltage channel capacitance HIGH-level input voltage LOW-level input voltage channel capacitance VI = 0 V; fi = 1 MHz
[2]
Conditions
Min
Typ[1]
Max
Unit
2.75 -
2.9 200 1.0
2.987 150 500 200 2 -
V V mV mA mA A A F
IO(reg) = 200 mA
0.65 x VCC VI = 0 V; fi = 1 MHz
[2]
-
0.3 20 0.3 20
V V pF V V pF
-
Memory card-side: pins CMD_SD and DATA0_SD to DATA3_SD 0.65 x VO(reg) -
Control and data outputs Host-side: pins CLK_FB, CMD_H and DATA0_H to DATA3_H VOH VOL VOH VOL ILRzd Rs Rpd Rpu HIGH-level output voltage LOW-level output voltage HIGH-level output voltage LOW-level output voltage Zener diode reverse leakage current series resistance pull-down resistance pull-up resistance IO = -3 mA; VI = VIH IO = 3 mA; VI = VIL IO = -6 mA; VI = VIH IO = 6 mA; VI = VIL VI = 3 V R1 to R6; tolerance 20 % R7; tolerance 30 % R10; tolerance 30 % R11 to R13; tolerance 30 % R14 and R15; tolerance 30 %
[1] [2] Typical values are measured at Tamb = 25 C. EMI filter line capacitance per data channel from I/O pin to driver; Cch is guaranteed by design.
VCC - 0.45 -
-
0.45 0.45 100 48 611 19.5 91 130
V V V V nA k k k k
Memory card-side: pins CLK_SD, CMD_SD and DATA0_SD to DATA3_SD, CD and WP VO(reg) - 0.45 32 329 10.5 49 70 40 470 15 70 100
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
7 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
9. Dynamic characteristics
Table 8. Voltage regulator Tamb = 25 C; unless otherwise specified. Symbol PSRR Parameter power supply rejection ratio Conditions VBAT = 3.0 V; Vripple(p-p) = 223.6 mV (0 dBm); Rsource = 50 fripple = 1 kHz fripple = 10 kHz tstartup(reg) regulator start-up time VCC = 1.8 V; VBAT = 3.0 V; IO(reg) = 200 mA; CL = 1 F; see Figure 3 40 30 200 dB dB s Min Typ Max Unit Voltage regulator output: pin VSD
VI ENABLE GND tstartup(reg) VO(reg) 50 %
regulator output 0V
97 %
001aah981
Measuring points: ENABLE signal at 0.5VCC and regulator output signal at 0.97VO(reg).
Fig 3.
Regulator start-up time
Table 9. Frequency response of integrated EMI filters Tamb = 25 C; unless otherwise specified. Symbol Parameter Clock, command and data channels[1] il insertion loss Rsource = 50 ; CL = 10 pF; RL = 50 fi = 401 MHz to 800 MHz fi = 801 MHz to 1.4 GHz fi = 1.4 GHz to 6.0 GHz
[1] Guaranteed by design.
Conditions
Min
Typ
Max
Unit
9 -
17 32
-
dB dB dB
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
8 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
Table 10. Output rise and fall times VBAT = 3.5 V; VO(reg) = 2.9 V; unless otherwise specified; transition time is the same as output rise time and output fall time; see Figure 4 for timing diagram and Figure 5 for test circuit. Symbol Parameter Conditions Min Typ Max Unit Memory card-side outputs: pins CLK_SD, CMD_SD and DATA0_SD to DATA3_SD Reference points at 70 % and 20 % tt transition time CL = 20 pF; RL = 100 k Tamb = +25 C; VCC = 1.8 V Tamb = -30 C; VCC = 1.9 V Tamb = +70 C; VCC = 1.62 V CL = 40 pF; RL = 100 k Tamb = +25 C; VCC = 1.8 V Tamb = -30 C; VCC = 1.9 V Tamb = +70 C; VCC = 1.62 V Reference points at 90 % and 10 % tt transition time CL = 20 pF; RL = 100 k Tamb = +25 C; VCC = 1.8 V Tamb = -30 C; VCC = 1.9 V Tamb = +70 C; VCC = 1.62 V Host-side outputs: pins CLK_FB, CMD_H and DATA0_H to DATA3_H Reference points at 70 % and 20 % tt transition time CL = 5 pF; RL = 100 k Tamb = +25 C; VCC = 1.8 V Tamb = -30 C; VCC = 1.9 V Tamb = +70 C; VCC = 1.62 V CL = 20 pF; RL = 100 k Tamb = +25 C; VCC = 1.8 V Tamb = -30 C; VCC = 1.9 V Tamb = +70 C; VCC = 1.62 V Reference points at 90 % and 10 % tt transition time CL = 5 pF; RL = 100 k Tamb = +25 C; VCC = 1.8 V Tamb = -30 C; VCC = 1.9 V Tamb = +70 C; VCC = 1.62 V 2.4 2.3 2.5 3.1 3.0 3.2 ns ns ns 1.7 1.4 1.8 2.9 2.5 3.0 ns ns ns 1.5 1.3 1.6 2.4 2.3 2.5 ns ns ns 3.0 2.9 3.7 4.2 4.1 4.9 ns ns ns 2.7 2.7 2.9 3.6 3.6 3.8 ns ns ns 1.5 1.5 1.8 2.5 2.5 2.8 ns ns ns
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
9 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
Table 11. Propagation delay of time domain response driver part VBAT = 3.5 V; VO(reg) = 2.9 V; Rsource = 50 ; propagation delay measurements include PCB delays and connectors; see Figure 4 for timing diagram and Figure 5 for test circuit. Symbol tPD Parameter propagation delay Conditions nominal case; Tamb = +27 C; VCC = 1.8 V CL = 20 pF CL = 40 pF best case; Tamb = -30 C; VCC = 1.9 V CL = 20 pF CL = 40 pF worst case; Tamb = +70 C; VCC = 1.62 V CL = 20 pF CL = 40 pF Memory card-side inputs to host-side outputs tPD propagation delay nominal case; Tamb = +27 C; VCC = 1.8 V CL = 5 pF CL = 20 pF best case; Tamb = -30 C; VCC = 1.9 V CL = 5 pF CL = 20 pF worst case; Tamb = +70 C; VCC = 1.62 V CL = 5 pF CL = 20 pF Host-side pins CLK_IN to CLK_FB tPD propagation delay nominal case; Tamb = +27 C; VCC = 1.8 V CL = 5 pF CL = 20 pF best case; Tamb = -30 C; VCC = 1.9 V CL = 5 pF CL = 20 pF worst case; Tamb = +70 C; VCC = 1.62 V CL = 5 pF CL = 20 pF
[1]
[1] [1] [1]
Min
Typ
Max
Unit
Host-side inputs to memory card-side outputs 6.2 7.3 5.7 6.5 6.7 7.5 7.0 8.2 6.5 7.5 7.8 8.8 7.8 9.1 7.3 8.5 8.9 10.1 ns ns ns ns ns ns
4.2 6.3 4 5.1 5.4 6.7
6.0 7.2 5.9 6.7 6.5 8.0
7.8 8.1 6.9 8.5 7.7 9.2
ns ns ns ns ns ns
7.6 8.2 6.7 7.6 8.5 9.1
9.2 9.9 8.1 8.8 10.7 11.4
10.7 11.6 9.5 10.5 12.9 13.9
ns ns ns ns ns ns
tPD is the same as HIGH-to-LOW propagation delay (tPHL) and LOW-to-HIGH propagation delay (tPLH).
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
10 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
VI A, B input GND tPHL VOH B, A output VOL VM
001aae967
VM
tPLH
Measuring points: host-side at 0.5VCC and memory card-side at 0.5VO(reg). VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
Output rise and fall times and data input to output propagation delay times (host-side to card-side or card-side to host-side) Table 12. Power dissipation per channel VCC = 1.8 V; VBAT = 4 V; all values are typical; memory card-side CL = 20 pF and host-side CL = 5 pF. Frequency (MHz) Data channel 1.0 10.0 20.0 50.0 Clock channel 1.0 10.0 20.0 50.0 Data channel 1.0 10.0 20.0 50.0
[1]
IBAT (mA)
ICC (mA)
P (mW)[1]
Host-side input to memory card-side output 0.79 3.30 5.79 12.3 0.44 3.1 5.4 12.2 0.002 0.020 0.037 0.090 0.05 0.59 0.97 2.36 3.16 13.3 23.2 49.4 1.85 13.5 23.4 53.1
Memory card-side input to host-side output 0.18 0.42 0.66 1.4 0.1 0.96 1.91 4.5 0.9 3.41 6.1 13.7
Power consumption is largely dependent on capacitive load connected to a driver output: P = VCC x ICC + VBAT x IBAT.
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
11 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
10. Test information
tW VI negative input 0V tf tr VI positive input 0V 20 % tW 70 % 50 % 50 % 70 % 50 % 20 % tr tf 50 %
VBAT VCC
VI VO
PULSE GENERATOR tr = tf = 1.8 ns
Rsource 50
DUT
Rterm CL RL
001aah982
Definitions test circuit: Rsource = source resistance of pulse generator. Rterm = termination resistance should be equal to output impedance Z0 of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance.
Fig 5.
Load circuitry for measuring switching time
11. Marking
bump A1 indicator
LASER MARKING AREA
001aah952
top view
Fig 6.
Marking of IP4853CX24
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
12 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
12. Package outline
WLCSP24: wafer level chip-size package; 24 bumps; 2.01 x 2.01 x 0.61 mm IP4853CX24
D
bump A1 index area A2 E A A1
detail X
e1 e b
E
e
D
C
e2
B
A 1 2 3 4 5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 0.66 0.61 0.56 A1 0.22 0.20 0.18 A2 0.44 0.41 0.38 b 0.29 0.26 0.23 D 2.06 2.01 1.96 E 2.06 2.01 1.96 e 0.4 e1 1.6 e2 1.6
OUTLINE VERSION IP4853CX24
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 08-04-14 09-06-11
Fig 7.
IP4853CX24_2
Package outline IP4853CX24 (WLCSP24)
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
13 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
13. Packing information
3 to 8 K
B-B
A
A0
P
D1 G
K0 5 max
W1 W
B0
B
B
F E
A
P2
0.05 / 40 P0
D0
T1 T
A-A
direction of feed
001aai051
Fig 8.
Tape and reel information Table 13. Tape dimensions Item tape width thickness distance Sprocket holes[1] diameter distance pitch Distance between center lines Compartments length direction width direction length width depth hole diameter pitch Device Carrier tape antistatic[2] Cover tape[3] Bending radius rotation film thickness width film thickness in winding direction Symbol W K G D0 E P0 P2 F A0 B0 K0 D1 P T W1 T1 R Specification (mm) Dimension Overall dimensions 8.00 1.20 0.75 1.50 1.75 4.00 2.00 3.50 2.20 2.20 0.80 0.50 4.00 20 0.25 5.75 0.1 30 Tolerance 0.1 max. min. +0.1 0.1 0.1 0.05 0.05 0.05 0.05 0.05 +0.1 0.1 max. 0.07 max. max. min.
Description
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
14 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
[1] [2] [3]
Cumulated pitch error: 0.2 mm per 10 pitches. Carbon loaded polystyrene 100 % recyclable. The cover tape shall not overlap the sprocket holes.
14. Design and assembly recommendations
14.1 PCB design guidelines
To achieve optimum performance it is recommended to use a Non-Solder Mask Design (NSMD) PCB design, also known as a copper defined design, incorporating laser-drilled micro-vias connecting the ground pads to a buried ground-plane layer. This results in the lowest possible ground inductance and provides the best high frequency and ESD performance. Refer to Table 14 for the recommended PCB design parameters.
Table 14. Recommended PCB design parameters 225 m diameter 100 m 335 m diameter 20 m to 40 m OSP FR4
PCB pad size Micro-via diameter Solder mask opening Copper thickness Copper finish PCB material
14.2 PCB assembly guidelines for Pb-free soldering
Table 15. Assemble recommendations 255 m diameter 100 m (0.004") SnAg[1]Cu[2] 50 : 50 see Figure 9 Solder screen aperture size Solder screen thickness Solder paste: Pb-free Solder/flux ratio Solder reflow profile
[1] [2] 3 to 4. 0.5 to 0.9.
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
15 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
T (C) Treflow(peak) 250 230 217 cooling rate
pre-heat
t1 t2
t3 t4 t5
t (s)
001aai161
The device is capable of withstanding at least three reflows of this profile.
Fig 9. Table 16. Symbol t1 t2 t3 t4 t5 dT/dt
Pb-free solder reflow profile Characteristics Parameter time 1 time 2 time 3 time 4 time 5 rate of change of temperature Conditions T = 0 C to +5 C soak time time from T = 25 C to Treflow(peak) time during T 250 C time during T 230 C time during T > 217 C cooling rate pre-heat Min 230 60 240 10 30 2.5 Typ Max 255 180 300 30 50 150 -6 4.0 Unit C s s s s s C/s C/s
Treflow(peak) peak reflow temperature
15. Abbreviations
Table 17. Acronym DUT EMI ESD FR4 MMC NSMD OSP PCB PSU Abbreviations Description Device Under Test ElectroMagnetic Interference ElectroStatic Discharge Flame Retard 4 MultiMediaCard Non-Solder Mask Design Organic Solderability Preservation Printed-Circuit Board Power Supply Unit
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
16 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
Abbreviations ...continued Description Restriction of Hazardous Substances Secure Digital Wafer Level Chip-Scale Package
Table 17. Acronym RoHS SD WLCSP
16. Revision history
Table 18. Revision history Release date 20090615 Data sheet status Product data sheet Change notice Supersedes IP4853CX24_1 Document ID IP4853CX24_2 Modifications:
* * * *
Table 11: Added minimum values and values for `host-side pins CLK_IN to CLK_FB'. Table 7: Changed maximum value for regulator quiescent current (not active mode). Table 8: Moved values from maximum to minimum for power supply rejection ratio. Removed /LF from all instances of type number IP4853CX24. Product data sheet -
IP4853CX24_1
20080722
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
17 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
IP4853CX24_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 15 June 2009
18 of 19
NXP Semiconductors
IP4853CX24
SD, MMC and microSD memory card integrated level shifter
19. Contents
1 1.1 1.2 1.3 2 2.1 2.2 3 4 5 5.1 6 7 8 9 10 11 12 13 14 14.1 14.2 15 16 17 17.1 17.2 17.3 17.4 18 19 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Logic control signals . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Packing information. . . . . . . . . . . . . . . . . . . . . 14 Design and assembly recommendations . . . 15 PCB design guidelines . . . . . . . . . . . . . . . . . . 15 PCB assembly guidelines for Pb-free soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 June 2009 Document identifier: IP4853CX24_2

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